K3N7C4000B-DC cmos mask rom pin name pin function a 0 - a 21 address inputs q 0 - q 15 data outputs oe output enable v cc power (+5v) v ss ground 64m-bit (4mx16) cmos mask rom the K3N7C4000B-DC is a fully static mask programmable rom organized 4,194,304 x 16 bit. it is fabricated using sili- con-gate cmos process technology. this device operates with a 5v single power supply, and all inputs and outputs are ttl compatible. because of its asynchronous operation, it requires no external clock assuring extremely easy operation. it is suitable for use in program memory of microprocessor and data memory, character generator. the K3N7C4000B-DC is packaged in a 42-dip. general description features 4,194,304 x 16 bit organization fast access time : 100ns(max.) : c l =50pf 120ns(max.) : c l =100pf supply voltage : single +5v current consumption operating : 70ma(max.) fully static operation all inputs and outputs ttl compatible three state outputs package -. K3N7C4000B-DC : 42-dip-600 a 21 x and decoder buffers a 0 y and decoder buffers memory cell sense amp. control logic matrix (4,194,304x16) buffers oe . . . . . . . . q 0 q 15 . . . pin configuration a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 21 v ss oe q 0 q 8 q 1 q 9 q 4 q 12 q 5 q 13 q 6 v ss q 14 q 7 q 15 dip K3N7C4000B-DC functional block diagram 1 2 3 4 42 41 5 6 40 39 7 8 38 37 9 10 36 35 11 12 34 33 13 14 32 31 15 16 30 29 17 18 27 28 19 20 25 24 21 23 22 q 2 q 10 q 3 q 11 a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 20 v cc 26
K3N7C4000B-DC cmos mask rom absolute maximum ratings note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to th e conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. item symbol rating unit voltage on any pin relative to v ss v in -0.3 to +7.0 v temperature under bias t bias -10 to +85 c storage temperature t stg -55 to +150 c recommended operating conditions (voltage reference to v ss , t a =0 to 70 c) item symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 0 0 0 v mode selection oe mode data power h operating high-z active l operating dout active capacitance (t a =25 c, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test conditions min max unit output capacitance c out v out =0v - 12 pf input capacitance c in v in =0v - 12 pf dc characteristics note : minimum dc voltage(v il ) is -0.3v an input pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input pins(v ih ) is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. parameter symbol test conditions min max unit operating current i cc cycle=5mhz, all outputs open oe =v il , v in =0.6v to 2.4v (ac test condition) - 70 ma input leakage current i li v in =0 to v cc - 10 m a output leakage current i lo v out =0 to v cc - 10 m a input high voltage, all inputs v ih 2.2 v cc +0.3 v input low voltage, all inputs v il -0.3 0.8 v output high voltage level v oh i oh =-400 m a 2.4 - v output low voltage level v ol i ol =2.1ma - 0.4 v
K3N7C4000B-DC cmos mask rom test conditions item value input pulse levels 0.6v to 2.4v input rise and fall times 10ns input and output timing levels 0.8v and 2.0v output loads 1 ttl gate and c l =50pf or 100pf ac characteristics (t a =0 c to +70 c, v cc =5v 10%, unless otherwise noted.) timing diagram read add a 0 ~a 21 oe d out add1 add2 valid data valid data t oh d 0 ~d 15 t df(note) t rc t oe t aa note : t df is defined as the time at which the outputs achieve the open circuit condition and is not referenced to v oh or v ol level. read cycle item symbol K3N7C4000B-DC10 (c l =50pf) K3N7C4000B-DC12 (c l =100pf) k3n4c1000b-dc15 (c l =100pf) unit min max min max min max read cycle time t rc 100 120 150 ns address access time t aa 100 120 150 ns output enable access time t oe 50 60 70 ns output or chip disable to output high-z t df 20 20 30 ns output hold from address change t oh 0 0 0 ns
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